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PTN3700
1.8 V simple mobile interface link bridge IC
Rev. 01 -- 14 August 2007 Product data sheet
1. General description
The PTN3700 is a 1.8 V simple mobile interface link bridge IC which can function both as a transmitter-serializer or a receiver-deserializer for RGB888 video data. When configured as transmitter (using input pin TX/RX), the PTN3700 serializes parallel CMOS video input data into 1, 2 or 3 subLVDS-based high-speed serial data channels. When configured as receiver, the PTN3700 deserializes up to 3 high-speed serial data channels into parallel CMOS video data signals. The parallel interface of the PTN3700 is based on the conventional and widely used 24-bit wide data bus for RGB video data, plus active LOW HS (Horizontal Synchronization) and VS (Vertical Synchronization) signals, and an active HIGH DE (Data Enable) signal. An additional two auxiliary bits A[1:0] are provided to permit signaling of miscellaneous status or mode information across the link to the display. The serial interface link of the PTN3700 is based on the open Simple Mobile Interface Link (SMILi) definition. In order to keep power low while accommodating various display sizes (e.g., up to 24-bit, 60 frames per second XVGA), the number of high-speed serial channels (`lanes') is configurable from 1 to 3 depending on the bandwidth needed. The data link speed is determined by the PCLK (Pixel Clock) rate and the number of serial channels selected. In order to maintain a low power profile, the PTN3700 has three power modes, determined by detection of an active input clock and by shutdown pin XSD. In Shutdown mode (XSD = LOW), the PTN3700 is completely inactive and consumes a minimum of current. In Standby mode (XSD = HIGH), the device is ready to switch to Active mode as soon as an active input clock signal is detected, and assume normal link operation. In Transmitter mode, the PTN3700 performs parity calculation on the input data (R[7:0], G[7:0], B[7:0] plus HS, VS and DE data bits) and adds an odd parity bit CP to the serial transmitted data stream. The PTN3700 in Receiver mode also integrates a parity checking function, which checks for odd parity across the decoded input word (R[7:0], G[7:0], B[7:0] plus HS, VS and DE data bits), and indicates whether a parity error has occurred on its CPO out pin (active HIGH). When a parity error occurs, the most recent error-free pixel data will be output instead of the received invalid pixel data. PTN3700 in Receiver mode offers an optional advanced frame mixing feature, which allows 18-bit displays to effectively display 24-bit color resolution by applying a patent-pending pixel data processing algorithm to the 24-bit video input data. One of two serial transmission methods is selectable: pseudo source synchronous transmission based on the pixel clock, or true source synchronous transmission based on the bit clock. The latter uses a patent-pending methodology characterized by zero overhead and operation guaranteed free from false pixel synchronization.
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
The PTN3700 automatically rotates the order of the essential signals (parallel CMOS and high-speed serial data and clock) depending on whether it is operating as transmitter or as receiver (using pin TX/RX). In addition, two Pinning Select bits (inputs PSEL[1:0]) allow for four additional signal order configurations. This allows for various topologies of printed circuit board or flex foil layout without crossing of traces; and enables the easy introduction of PTN3700 into an existing `parallel' design avoiding board re-layout. The PTN3700 is available in a 56-ball VFBGA package and operates across a temperature range of -40 C to +85 C.
2. Features
I Configurable as either Transmitter or Receiver I One of two serial transmission methods selectable (pixel clock referenced pseudo source synchronous or bit clock referenced true source synchronous) I 3 differential subLVDS high-speed serial lanes I One differential pixel clock I Configurable aggregate data bandwidth allowing up to 24-bit color, 60 fps XGA: N 1 lane at 30x serialization rate up to 650 Mbit/s N 2 lanes at 15x serialization rate up to 1300 Mbit/s N 3 lanes at 10x serialization rate up to 1.95 Gbit/s I Parity encoding (transmitter) and detection (receiver) with last valid pixel repetition I Advanced Frame Mixing function (in Receiver mode) for 24-bit color depth using conventional 18-bit displays or specially adapted `18-bit plus' displays I Parallel CMOS I/O based on interface definition of RGB888 plus HS, VS, DE I Very low power profile: N Shutdown mode for minimum idle power (< 3 A typical) N Low-power Standby mode with input clock frequency auto-detect (< 3 A typical) N Low active transmitter power: 18 mW (typ.) for QVGA1 and 40 mW (typ.) for WVGA2 N Low active receiver power: 15 mW (typ.) for QVGA and 36 mW (typ.) for WVGA I Slew rate control on receiver parallel CMOS outputs I Operates from a single 1.8 V 150 mV power supply I Configurable mirroring pinout (dependent on Tx or Rx mode and PSEL[1:0] inputs) for optimum single layer flex-foil flow-through in various application scenarios I Available in 56-ball VFBGA package
3. Applications
I High-resolution mobile phones I Portable applications with video display capability
1. 2.
QVGA: 240 x 320 pixels at 60 Hz frame rate; 20 % non-active display data overhead; PCLK at 5.5 MHz; one-lane operation at 166 Mbit/s; 24-bit color data. WVGA: 854 x 480 pixels at 60 Hz frame rate; 20 % non-active display data overhead; PCLK at 29.5 MHz; two-lane operation at 885.4 Mbit/s; 24-bit color data.
(c) NXP B.V. 2007. All rights reserved.
PTN3700_1
Product data sheet
Rev. 01 -- 14 August 2007
2 of 41
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
4. Ordering information
Table 1. Ordering information Solder process Package Name PTN3700EV/G Description Version SOT991-1 Type number
Pb-free (SnAgCu VFBGA56 plastic very thin fine-pitch ball grid array package; solder ball compound) 56 balls; body 4 x 4.5 x 0.65 mm[1]
[1]
0.5 mm ball pitch; 1.0 mm maximum package height.
4.1 Ordering options
Table 2. Ordering options Topside mark 3700 Temperature range -40 C to +85 C Type number PTN3700EV/G
5. Functional diagram
VDD VDDA
PTN3700
R[7:0] G[7:0] B[7:0] HS VS DE A[1:0]
2 8 8 8
D0+ D0- PROTOCOL MAPPING, PARITY ENCODING, SYNC WORD ENCODING
INPUT REGISTER
SERIALIZER
D1+ D1-
D2+ D2-
N x PCLK PCLK PLL 1 x PCLK
/2
1 0 FSS
CLK+ CLK-
FSS XSD LS[1:0] PSEL[1:0]
2 2
CONFIGURATION AND POWER MANAGEMENT
TX/RX = HIGH GND GNDA
002aab363
Fig 1. Functional diagram of PTN3700 in Transmitter mode
PTN3700_1
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Product data sheet
Rev. 01 -- 14 August 2007
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NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
VDD
VDDA
PTN3700
D0+
8 8
R[7:0] G[7:0] B[7:0] HS VS DE
D0- D1+ DESERIALIZER D1- D2+
2
PROTOCOL PARSING, PARITY DETECTION, ADVANCED FRAME MIXING, SYNC WORD DECODING
8
OUTPUT REGISTER
A[1:0]
D2-
N x PCLK 0 PLL PCLK 1 DDR SDR FSS CPO
CLK+
CLK-
FM FSS F/XS XSD LS[1:0] PSEL[1:0]
2 2
CONFIGURATION AND POWER MANAGEMENT
TX/RX = LOW GND GNDA
002aab364
Fig 2. Functional diagram of PTN3700 in Receiver mode
PTN3700_1
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Product data sheet
Rev. 01 -- 14 August 2007
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NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
6. Pinning information
6.1 Pinning
ball A1 index area
PTN3700EV/G
1234567
A B C D E F G H
002aac377
Transparent top view
Fig 3. Ball configuration for VFBGA56
1 A B C D E F G H D2+ D2- D1+ D1- CLK+ CLK- D0+ D0-
2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO
3 DE VS A1 PSEL0 PSEL1 A0 R6 R7
4 HS PCLK GND LS0 LS1 GND R4 R5
5 B0 B1 VDD FM FSS VDD R2 R3
6 B2 B3 B6 G0 G2 G4 R0 R1
7 B4 B5 B7 G1 G3 G5 G6 G7
002aac378
1 A B C D E F G H D2+ D2- D1+ D1- CLK+ CLK- D0+ D0-
2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO
3 DE VS A1 PSEL0 PSEL1 A0 B1 B0
4 HS PCLK GND LS0 LS1 GND B3 B2
5 R7 R6 VDD FM FSS VDD B5 B4
6 R5 R4 R1 G7 G5 G3 B7 B6
7 R3 R2 R0 G6 G4 G2 G1 G0
002aac379
56-ball, 7 x 8 grid; transparent top view
56-ball, 7 x 8 grid; transparent top view
Fig 4. VFBGA56 ball mapping - Transmitter mode (TX/RX = HIGH); PSEL[1:0] = 00b
1 A B C D E F G H D0- D0+ CLK- CLK+ D1- D1+ D2- D2+ 2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO 3 DE VS A1 PSEL0 PSEL1 A0 R6 R7 4 HS PCLK GND LS0 LS1 GND R4 R5 5 B0 B1 VDD FM FSS VDD R2 R3 6 B2 B3 B6 G0 G2 G4 R0 R1 7 B4 B5 B7 G1 G3 G5 G6 G7
002aac380
Fig 5. VFBGA56 ball mapping - Transmitter mode (TX/RX = HIGH); PSEL[1:0] = 01b
1 A B C D E F G H D0- D0+ CLK- CLK+ D1- D1+ D2- D2+ 2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO 3 DE VS A1 PSEL0 PSEL1 A0 B1 B0 4 HS PCLK GND LS0 LS1 GND B3 B2 5 R7 R6 VDD FM FSS VDD B5 B4 6 R5 R4 R1 G7 G5 G3 B7 B6 7 R3 R2 R0 G6 G4 G2 G1 G0
002aac381
56-ball, 7 x 8 grid; transparent top view
56-ball, 7 x 8 grid; transparent top view
Fig 6. VFBGA56 ball mapping - Transmitter mode (TX/RX = HIGH); PSEL[1:0] = 10b
PTN3700_1
Fig 7. VFBGA56 ball mapping - Transmitter mode (TX/RX = HIGH); PSEL[1:0] = 11b
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 14 August 2007
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NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
1 A B C D E F G H D2+ D2- D1+ D1- CLK+ CLK- D0+ D0-
2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO
3 R7 R6 A1 PSEL0 PSEL1 A0 VS DE
4 R5 R4 GND LS0 LS1 GND PCLK HS
5 R3 R2 VDD FM FSS VDD B1 B0
6 R1 R0 G5 G3 G1 B7 B3 B2
7 G7 G6 G4 G2 G0 B6 B5 B4
002aac382
1 A B C D E F G H D2+ D2- D1+ D1- CLK+ CLK- D0+ D0-
2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO
3 B0 B1 A1 PSEL0 PSEL1 A0 VS DE
4 B2 B3 GND LS0 LS1 GND PCLK HS
5 B4 B5 VDD FM FSS VDD R6 R7
6 B6 B7 G2 G4 G6 R0 R4 R5
7 G0 G1 G3 G5 G7 R1 R2 R3
002aac383
56-ball, 7 x 8 grid; transparent top view
56-ball, 7 x 8 grid; transparent top view
Fig 8. VFBGA56 ball mapping - Receiver mode (TX/RX = LOW); PSEL[1:0] = 00b
1 A B C D E F G H D0- D0+ CLK- CLK+ D1- D1+ D2- D2+ 2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO 3 R7 R6 A1 PSEL0 PSEL1 A0 VS DE 4 R5 R4 GND LS0 LS1 GND PCLK HS 5 R3 R2 VDD FM FSS VDD B1 B0 6 R1 R0 G5 G3 G1 B7 B3 B2 7 G7 G6 G4 G2 G0 B6 B5 B4
002aac384
Fig 9. VFBGA56 ball mapping - Receiver mode (TX/RX = LOW); PSEL[1:0] = 01b
1 A B C D E F G H D0- D0+ CLK- CLK+ D1- D1+ D2- D2+ 2 VDDA GNDA TX/RX VDD GND F/XS XSD CPO 3 B0 B1 A1 PSEL0 PSEL1 A0 VS DE 4 B2 B3 GND LS0 LS1 GND PCLK HS 5 B4 B5 VDD FM FSS VDD R6 R7 6 B6 B7 G2 G4 G6 R0 R4 R5 7 G0 G1 G3 G5 G7 R1 R2 R3
002aac385
56-ball, 7 x 8 grid; transparent top view
56-ball, 7 x 8 grid; transparent top view
Fig 10. VFBGA56 ball mapping - Receiver mode (TX/RX = LOW); PSEL[1:0] = 10b
Fig 11. VFBGA56 ball mapping - Receiver mode (TX/RX = LOW); PSEL[1:0] = 11b
PTN3700_1
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Product data sheet
Rev. 01 -- 14 August 2007
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PTN3700
1.8 V simple mobile interface link bridge IC
6.2 Pin description
Table 3. Symbol Parallel data inputs R[7:0], G[7:0], B[7:0] HS VS DE A0, A1 High-speed serial outputs D0+, D0-, D1+, D1-, D2+, D2- CLK+, CLK- Clock inputs PCLK Configuration inputs TX/RX LS0, LS1 PSEL0, PSEL1 XSD CMOS CMOS CMOS CMOS Transmitter/Receiver configuration input pin. When HIGH, PTN3700 is configured as transmitter. Serialization mode program pins. Select between 1, 2 or 3 lanes. See Table 5. Pin mirroring select pins. See Table 6 and Table 7 Shutdown mode input pin, active LOW, puts PTN3700 in lowest-power mode by deactivating all circuitry. When HIGH, PTN3700 is either in Active mode or awaiting clock input (Standby mode) Fully Source Synchronous select pin. When LOW, PTN3700 uses pseudo source synchronous serial transmission mode with the pixel clock as both the reference frequency and the frame boundary delineation. When HIGH, PTN3700 uses true source synchronous transmission with a serial Double Data Rate (DDR) bit clock for the serial data. Embedded synchronization words are encoded for pixel synchronization. On both Receiver and Transmitter, the settings of the FSS pin should match. Otherwise the link will not function. power supply voltage analog (PLL) power supply voltage analog (PLL) ground ground Signals are inactive in Transmitter mode and should be tied down to GND. CMOS Pixel clock reference input SubLVDS driver SubLVDS driver Serialized high-speed differential subLVDS data outputs Serialized high-speed differential subLVDS clock outputs CMOS CMOS CMOS CMOS CMOS 8-bit wide R, G, B pixel data inputs Horizontal synchronization data input, active LOW Vertical synchronization data input, active LOW Data Enable input, active HIGH Auxiliary input bits Pin description - Transmitter mode Pin[1] Type Description
FSS
CMOS
Power supply VDD VDDA GNDA GND Miscellaneous CPO, FM, F/XS
[1] Depends on configuration.
power power ground ground CMOS
PTN3700_1
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Product data sheet
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NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
Table 4. Symbol
Pin description - Receiver mode Pin[1] Type CMOS CMOS CMOS CMOS CMOS Description 8-bit wide R, G, B pixel data outputs Horizontal synchronization data output, active LOW Vertical synchronization data output, active LOW Data Enable output, active HIGH Auxiliary output bits
Parallel data outputs R[7:0], G[7:0], B[7:0] HS VS DE A0, A1 High-speed serial inputs D0+, D0-, D1+, D1-, D2+, D2- CLK+, CLK- Clock outputs PCLK Configuration inputs TX/RX LS0, LS1 PSEL0, PSEL1 XSD CMOS CMOS CMOS CMOS Transmitter/Receiver configuration input pin. When LOW, PTN3700 is configured as receiver. Serialization mode program pins. Select between 1, 2 or 3 lanes. See Table 5. Pin mirroring select pins. See Table 6 and Table 7. Shutdown mode input pin, active LOW, puts PTN3700 in lowest-power mode by deactivating all circuitry. When HIGH, PTN3700 is either in Active mode or awaiting clock input (Standby mode). Program pin for fast (F/XS = HIGH) or slow (F/XS = LOW) parallel output and PCLK slew rate Frame Mixing select pin. When LOW, Frame Mixing is disabled and PTN3700 passes 24-bit video data transparently. When HIGH, Frame Mixing is enabled and PTN3700 applies processing to the 24-bit video data resulting in 18-bit output data words encoded with 24-bit color depth. Frame Mixing is only available in Receiver mode. Fully Source Synchronous select pin. When LOW, PTN3700 uses pseudo source synchronous serial reception mode with the pixel clock as both the reference frequency and the frame boundary delineation. When HIGH, PTN3700 uses true source synchronous reception with embedded synchronization word decoding, with the bit clock as reference frequency. On both Receiver and Transmitter, the settings of the FSS pin should match. Otherwise the link will not function. Parity error output, active HIGH. A HIGH level indicates a parity error was detected in the current pixel data power supply voltage analog (PLL) power supply voltage analog (PLL) ground ground CMOS Pixel clock output SubLVDS Serialized high-speed differential subLVDS data inputs receiver SubLVDS Serialized high-speed differential subLVDS clock inputs receiver
F/XS FM
CMOS CMOS
FSS
CMOS
Parity output CPO Power supply VDD VDDA GNDA GND
[1] Depends on configuration.
CMOS
PTN3700_1
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PTN3700
1.8 V simple mobile interface link bridge IC
7. Functional description
7.1 General
A complete simple mobile interface link consists of one PTN3700 configured as transmitter (see Figure 1); two, three or four differential-pair high-speed signaling channels; and one PTN3700 configured as receiver (see Figure 2). Link power and ground are supplied to pins VDD and GND respectively (power and ground should be routed and decoupled to analog supply pin VDDA and ground pin GNDA separately for lowest jitter operation). Configuration of either transmitter or receiver mode is achieved by strapping the CMOS input pin TX/RX HIGH or LOW, respectively. Configured as transmitter, PTN3700 accepts parallel CMOS input data including color pixel data (R[7:0], G[7:0], B[7:0]), three control bits HS (horizontal synchronization), VS (vertical synchronization), DE (data enable), auxiliary bits A[1:0] and pixel clock PCLK. The PTN3700 calculates a parity bit (excluding the auxiliary bits, see Section 7.6) and serializes the data and outputs as a high-speed serial data stream on up to three subLVDS differential outputs (D0+, D0-, D1+, D1-, D2+, D2-) depending on the serialization mode selected by pins LS[1:0] (see Section 7.2). An integrated low-jitter PLL generates internally the bit clock used for serialization of video input data, parity bit and control bits, and outputs along with the serial output data a differential pixel clock on differential subLVDS output pair CLK+ and CLK-. Configured as receiver, PTN3700 accepts serial differential data inputs D0+, D0-, D1+, D1-, D2+, D2- and differential input clock CLK+ and CLK- from the signaling channel and deserializes the received data into parallel output data on pins R[7:0], G[7:0], B[7:0], HS, VS, DE and A[1:0] along with the PLL-regenerated pixel clock PCLK. Also, a parity checking function is performed on the incoming R[7:0], G[7:0], B[7:0], HS, VS, DE bits and an error flagged by signaling a HIGH state on CMOS output pin CPO (see Section 7.6). Serialization mode pins LS[1:0] need to be selected according to the expected serialization mode (see Section 7.2) to correctly receive and decode the up to three subLVDS differential serial inputs. To minimize EMI, the parallel outputs can be configured by tying pin F/XS either HIGH or LOW to output fast or slow output slew rates respectively. The PTN3700 is capable of operating in either of two distinct transmission modes: Pseudo Source Synchronous mode (PSS), and Full (or `true') Source Synchronous mode (FSS), selected by CMOS input pin FSS. In PSS mode, the pixel clock PCLK is used both as the transmission frequency reference and its rising edge as the delineation of the start of a pixel. This transmission mode relies on the Receiver PLL to reconstruct the bit clock at the receiving end. In FSS mode, the bit clock is transmitted (in DDR mode) instead of the pixel clock. Rather than achieve frame boundary detection using the pixel clock edge as in PSS mode, in FSS mode the Transmitter encodes `synchronization words' over the link which are detected and used for data to pixel alignment by the Receiver. This methodology guarantees false-synchronization-free transmission with zero protocol overhead. The PTN3700 can be put into very low `Shutdown' power state by tying CMOS input pin XSD LOW. Additionally, the PTN3700 will automatically enter a low-power `Standby' mode when no active input clock is detected on its inputs (see Section 7.5).
PTN3700_1
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Product data sheet
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PTN3700
1.8 V simple mobile interface link bridge IC
7.2 Link programmability
The number of high-speed serial channels used is programmed by CMOS input pins LS[1:0]. For a given link consisting of a transmitter and receiver pair of PTN3700's, the number of channels used must be programmed identically or the link will malfunction. The PTN3700, once programmed, will assume the corresponding serialization ratio as shown in Table 5. When pins LS[1:0] are both HIGH, the PTN3700 is put in a test mode which is used for production testing purposes only and should not be used in application. The 1-lane mode is typically meant for smaller video display formats (e.g., QVGA to HVGA), while the 2-lane mode is typically used for display formats like HVGA and VGA. The 3-lane mode supports larger display formats such as VGA or XGA. Please see Section 12.1 for more information.
Table 5. LS1 Link programmability LS0 Mode Number of high-speed serial channels 1 2 3 reserved[1] Supported PCLK frequency range (MHz) 4.0 to 21.6 8.0 to 43.3 20.0 to 65.0 reserved Guaranteed data bandwidth per channel (Mbit/s) 120 to 650 120 to 650 200 to 650 reserved Guaranteed aggregate link bandwidth (Mbit/s) 650 1300 1950 reserved
L L H H
[1]
L H L H
00 01 10 11
Mode 11 is used for test purposes only.
7.3 Versatile signal mirroring programmability
In order to provide flexibility for different signal order and flow requirements in different applications, the PTN3700 can be programmed to mirror its signal order for the parallel and serial I/Os independently using the PSEL[1:0] inputs. The signal order also changes as a function of the TX/RX input by mirroring signals in such a way that the Transmitter and Receiver in a given link can be connected without signal crossings by simply opposing the two instances of PTN3700 and rotating one of them by 180 degrees. The truth table for the versatile signal mirroring scheme is shown in Table 6 and Table 7. The individual ball mappings are given in Figure 4 through Figure 11.
PTN3700_1
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Product data sheet
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PTN3700
1.8 V simple mobile interface link bridge IC
Versatile signal mirroring programmability - Parallel I/O TX/RX L PSEL0 L H DE VS HS PCLK R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 L R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 PCLK HS VS DE H B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 PCLK HS VS DE (Receive mode) (Transmit mode) H
Table 6.
Ball location[1]
H3 G3 H4 G4 H5 G5 H6 G6 H7 G7 F7 F6 E7 E6 D7 D6 C7 C6 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3
[1]
DE VS HS PCLK B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7
For PTN3700EV/G VFBGA56 package option. See also Figure 4 through Figure 11.
PTN3700_1
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Product data sheet
Rev. 01 -- 14 August 2007
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NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
Versatile signal mirroring programmability - Serial I/O PSEL1 L H D0- D0+ CLKCLK+ D1- D1+ D2- D2+ D2+ D2- D1+ D1- CLK+ CLK- D0+ D0-
Table 7.
Ball location[1] A1 B1 C1 D1 E1 F1 G1 H1
[1]
For PTN3700EV/G VFBGA56 package option. See also Figure 4 through Figure 11.
7.4 High-speed data channel protocol options
The PTN3700 maps the transmission protocol in accordance with the serialization mode selected by pins LS[1:0]. In Mode 00 (1-channel), all RGB, parity and synchronization bits are serialized onto a single 30-bit sequence. In Mode 01 (2-channel), these bits are mapped onto two simultaneous 15-bit sequences divided across two lanes. In Mode 10 (3-channel), the 30 bits are serialized onto three simultaneous 10-bit sequences. The serial bit mapping is different between pseudo-source-synchronous mode (FSS = LOW) and fully source-synchronous mode (FSS = HIGH). The mapping of the data bits in pseudo-source synchronous mode is shown in Figure 12, Figure 13 and Figure 14. (Note that the CLK in Mode 01 has an asymmetrical duty cycle of 8/15). The serial bit mapping in fully source-synchronous mode is shown in Figure 15, Figure 16 and Figure 17. Note that the fully source synchronous transmission mode is not dependent on the phase of PCLK for receiver synchronization.
PTN3700_1
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Product data sheet
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NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
7.4.1 Serial protocol bit mapping - pseudo source synchronous mode (FSS = LOW)
D0 (differential)
R7
R6
R1
R0
G7
G6
G1
G0
B7
B6
B1
B0
VS
HS
DE
A1
A0
CP
R7
CLK (differential) 1 / fo(PCLK) or 1 / fi(PCLK)
002aac862
Fig 12. Mode 00 - single serial data channel mode (FSS = LOW)
D0 (differential)
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
VS
A0
CP
R7
R6
D1 (differential)
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
HS
DE
A1
G3
G2
CLK (differential) 1 / fo(PCLK) or 1 / fi(PCLK)
002aac863
Fig 13. Mode 01 - dual serial data channel mode (FSS = LOW)
D0 (differential)
R7
R6
R5
R4
R3
R2
R1
R0
VS
CP
R7
R6
D1 (differential)
G7
G6
G5
G4
G3
G2
G1
G0
HS
A0
G7
G6
D2 (differential)
B7
B6
B5
B4
B3
B2
B1
B0
DE
A1
B7
B6
CLK (differential) 1 / fo(PCLK) or 1 / fi(PCLK)
002aac864
Fig 14. Mode 10 - triple serial data channel mode (FSS = LOW)
PTN3700_1
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Product data sheet
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NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
7.4.2 Serial protocol bit mapping - fully source synchronous mode (FSS = HIGH)
D0 (differential)
DE
HS
VS
R0
R1
R7
G0
G1
G7
B0
B1
B5
A0
A1
B6
B7
CP
DE
CLK (differential) 1 / fo(PCLK) or 1 / fi(PCLK)
002aac871
Fig 15. Mode 00 - single serial data channel mode (FSS = HIGH)
D0 (differential)
DE
HS
VS
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
DE
D1 (differential)
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
A0
A1
B6
B7
CP
G4
CLK (differential) 1 / fo(PCLK) or 1 / fi(PCLK)
002aac872
Fig 16. Mode 01 - dual serial data channel mode (FSS = HIGH)
D0 (differential)
DE
HS
VS
R0
R1
R2
R3
R4
R5
R6
DE
D1 (differential)
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
R7
D2 (differential)
B1
B2
B3
B4
B5
A0
A1
B6
B7
CP
B1
CLK (differential) 1 / fo(PCLK) or 1 / fi(PCLK)
002aac873
Fig 17. Mode 10 - triple serial data channel mode (FSS = HIGH)
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7.4.3 PLL, PCLK, CLK and pixel synchronization
7.4.3.1 Pixel synchronization PSS mode: The serial clock CLK provides the word boundaries explicitly for frame synchronization. At the receiver side, a PLL is needed to re-generate the bit clock, translating to a higher receiver power dissipation. FSS mode: The serial clock CLK is truly synchronous with the serial data. Embedded synchronization words are transmitted in the non-active display area for pixel synchronization. The receiver PLL is powered down during this mode, hence the lower power consumption when compared with PSS mode. The special embedded synchronization words are guaranteed by design to never trigger false synchronization. 7.4.3.2 PLL The PLL locks onto the PCLK input during transmit mode or the CLK input during receiver mode. It generates an internal high-speed clock, which is phase-aligned to the input clock. The PLL logic uses the lane select and transmit/receive status to determine the necessary PLL bandwidth settings and PLL divider values automatically. The PLL is able to track spread spectrum clocking to reduce EMI. The spread spectrum clock modulation frequency can be from 30 kHz to 33 kHz. Transmitter: The internally generated clock is always aligned to the input clock PCLK.
* PSS mode: Refer to Section 7.4.1. * FSS mode: The output clock CLK is Double Data Rate (DDR) and both clock edges
are aligned to the data output. Receiver:
* PSS mode: The PLL generates an internal clock at serial bit frequency and locks to
the input clock CLK.
* FSS mode: The receiver uses Double Data Rate (DDR) input clock CLK, which is
aligned to the data already.
7.4.4 HS, VS and DE signal usage in various PTN3700 modes
When frame mixing is not used in PSS mode, VS, HS, DE, R[7:0], G[7:0], B[7:0] are treated as arbitrary user data. In this mode, PTN3700 functions as a pure serializer and deserializer, and is unaware of the meaning or polarity of VS, HS, DE, R[7:0], G[7:0], B[7:0]. In FSS mode, PTN3700 makes use of VS, HS and DE to implement pixel synchronization with embedded sync words in the non-active display area. When frame mixing is used, VS, HS, DE and R[7:0], G[7:0], B[7:0] are used to implement NXP-patented frame mixing algorithm. Table 8 summarizes the requirements of VS, HS, DE and RGB in various modes.
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VS, HS, DE, and RGB requirements[1][2] Mode PSS FSS FM HIGH LOW HIGH LOW VS, HS active LOW X active LOW active LOW DE active HIGH X active HIGH active HIGH R, G, B R, G, B X R, G, B X A[1:0] X X X X
Table 8. FSS LOW HIGH
[1] [2]
`X' signifies that PTN3700 handles this signal transparently, i.e., data is transmitted and received as-is. `R, G, B' signifies that R, G, B video data have to be input according to the exact chosen pin configuration of PTN3700, specifically: a) Bit order reversal is not allowed, even if both the transmit data and receive data are reversed in bit order. For example, the MSB of `R' color from video source must be input as `R7'. b) `R' must be used for red color, `G' for green color, and `B' for blue color.
7.4.4.1
PSS mode HS, VS and DE are treated by PTN3700 in the same way as RGB signals in PSS mode; that is, HS, VS, and DE are serialized and transmitted transparently by the PTN3700 transmitter, and transparently received and deserialized by PTN3700 receiver. Data Enable (DE) signal is typically used to signify the active display area from the non-active display area. In the case that advanced frame mixing is not used:
* DE signal can be tied HIGH or LOW, for displays not using DE signal. * HS and VS can be active HIGH or active LOW.
7.4.4.2 FSS mode In FSS mode, PTN3700 uses true source synchronous transmission with a serial Double Data Rate (DDR) bit clock for the serial data. FSS mode requires the following operating conditions:
* Active LOW HS * Active LOW VS * Active HIGH DE
In FSS mode, DE = 1 means active video, and PTN3700 generates embedded sync words when DE = 0. DE, VS and HS must be actively driven according to the typical video screen figure shown in Figure 18.
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HS = 0 HS = 1 000 001 010 011 010 011 active video 001 011 111 011 VS = 1 010 011 VS = 0
001
011
011
011
002aac803
3 numbers correspond to [DE, HS, VS]
Fig 18. Typical video screen
7.5 Power modes
The PTN3700 has three different power modes to minimize power consumption of the link as a function of link activity: Shutdown mode, Standby mode, and Active mode. The truth table for the three power modes is shown in Table 9 and Table 10.
* Shutdown mode: By driving input pin XSD LOW, the PTN3700 assumes lowest
power mode. All internal logic circuits are reset during this mode, and the link is completely inactive. The transmitter high-speed serial output channels are put in high-impedance state, and the receiver high-speed serial input channels are pulled LOW. The receiver CMOS parallel outputs will all be set HIGH with the exception of DE and PCLK which are reset LOW. However, the input buffers for the transmitter remain active, so it is recommended to stop PCLK and RGB data to achieve the lowest Shutdown mode power.
* Standby mode: When pin XSD is set HIGH but no input clock is active, the PTN3700
detects inactivity of the clock3 and remains in a low-power Standby mode until an active input clock is detected. The transmitter serial outputs, receiver serial inputs and receiver parallel outputs all behave identically to their respective states in Shutdown mode.
* Active mode: When pin XSD is set HIGH and an active input clock is detected,
PTN3700 will assume normal link operation. Current consumption depends on the PCLK frequency, number of lanes, FSS/PSS mode, data pattern, etc.
Table 9. Inputs XSD L H H PCLK X stopped running Shutdown Standby Active Power modes - Transmitter mode Power mode Outputs D0+, D0-, D1+, D1-, D2+, D2- high-Z high-Z active serial data CLK+, CLK- high-Z high-Z active
3.
The PTN3700 clock detection circuit identifies the clock as inactive when the PCLK input signal frequency is less than 500 kHz.
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Power modes - Receiver mode Data Outputs R[7:0], G[7:0], B[7:0], HS, VS H H active data DE, PCLK L L active
Table 10. Inputs XSD L H H
State of serial data inputs Power D0+, D0-, D1+, D1-, D2+, D2- mode CLK+, CLK- X or floating stopped running resistively pulled H or L resistively pulled H or L normal receiver state Shutdown Standby Active
7.6 Link error detection and correction
In Transmitter mode, PTN3700 calculates an odd parity bit and merges this into the serialized output data stream to allow the receiver to detect whether parity has been violated for its received input data. The parity bit CP is calculated across the 27-bit input data word (R[7:0], G[7:0], B[7:0], HS, VS and DE) for every pixel transmitted, as shown in Table 11. Note that the auxiliary bits A[1:0] are excluded from the parity calculation.
Table 11. XSD H H H L Parity encoding function table - Transmitter mode Inputs PCLK running running stopped X or floating of inputs = H (R[7:0], G[7:0], B[7:0], HS, VS, DE) odd even X or floating X or floating Encoded parity bit CP L H undefined undefined
In Receiver mode, the received encoded parity bit CP is compared against the received 27-bit input data word (R[7:0], G[7:0], B[7:0], HS, VS and DE) for every pixel, and an error is flagged by setting parity error output CPO HIGH for the duration of the pixel clock period in which the error was detected. Note that the auxiliary output bits A[1:0] are excluded from the parity detection. In addition, during the pixel clock period in which the error occurs, the last valid pixel word is output to R[7:0], G[7:0], B[7:0], HS, VS and DE instead of the current erroneous pixel data. The last valid pixel word is defined as the data prior to the first parity error detected in any concatenation of parity errors. If a parity error is detected but no valid previous pixel information is available, the receiver will output values R[7:0] = G[7:0] = B[7:0] = HS = VS = HIGH, and DE = LOW. The truth table for receiver parity function is shown in Table 12. Note that the auxiliary bits A[1:0] are not affected by the last valid pixel repetition.
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Table 12.
Parity decoding function table - Receiver mode Inputs Received parity bit CP L L H H X X Parity output CPO L H H L L L Data outputs R[7:0], G[7:0], B[7:0], HS, VS, DE[1][2] RGBn, HSn, VSn, DEn RGB0, HS0, VS0, DE0 RGB0, HS0, VS0, DE0 RGBn, HSn, VSn, DEn undefined undefined
XSD H H H H H L
[1] [2]
Clock running running running running stopped X or floating
of bits received in frame = H (R[7:0], G[7:0], B[7:0], HS, VS, DE) odd even odd even X or floating X or floating
YYYn = current valid pixel data is output to the parallel interface. YYY0 = most recent valid pixel data is output to the parallel interface.
7.7 Frame Mixing and Advanced Frame Mixing
When PTN3700 is configured as Receiver (TX/RX = LOW), the CMOS input FM selects whether the Frame Mixing function is turned on (FM = HIGH) or off (FM = LOW). (When PTN3700 is configured as Transmitter (TX/RX = HIGH), the Frame Mixing function is not available, and the FM input should not be used.) Advanced Frame Mixing is a proprietary pixel mapping algorithm that features the ability to render full 24-bit color resolution (provided 24-bit source data is input) using an 18-bit or an 18-bit plus display. When Frame Mixing is off, the full 24-bit data path is maintained unaltered for the link (transparent). When Frame Mixing is enabled, the algorithm maps the incoming 24-bit data to the 18-bit output data, aligned to the MSB. This is illustrated in Table 13. The new 18-bit data fields (R[7:2]FM, G[7:2]FM and B[7:2]FM) contain the altered information as calculated by the Frame Mixing algorithm from the original data. One additional `Advanced Frame Mixing' bit is encoded into the next lower significant bit (R1AFM, G1AFM and B1AFM) of the output data.
Table 13. Bit Input data Advanced Frame Mixing bit mapping (FM = HIGH) 7 R7 G7 B7 Output data R7FM G7FM B7FM 6 R6 G6 B6 R6FM G6FM B6FM 5 R5 G5 B5 R5FM G5FM B5FM 4 R4 G4 B4 R4FM G4FM B4FM 3 R3 G3 B3 R3FM G3FM B3FM 2 R2 G2 B2 R2FM G2FM B3FM 1 R1 G1 B1 R1AFM G1AFM B1AFM 0 R0 G0 B0 HIGH HIGH HIGH
When using Frame Mixing with normal 18-bit displays, the 6 MSBs of the parallel video data outputs (R[7:2], G[7:2] and B[7:2]) should be connected to the display driver inputs. When using special `18-bit plus' display drivers (Advanced Frame Mixing capable), additionally the next lower significant bit (R1, G1 and B1) should be connected to the corresponding display driver input.
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7.8 Auxiliary signals
The two auxiliary bits A[1:0] are user-supplied bits that can be additionally serialized and deserialized by the PTN3700 in transmitter and receiver modes, respectively. These auxiliary bits are transparent to the PTN3700 and can be used to transmit and receive miscellaneous status or mode information across the link to the display. Note that the auxiliary bits A[1:0] are excluded from the parity calculation and detection in the transmitter and receiver modes respectively. Even in the event of parity error being detected in the receiver mode, A[1:0] will still be deserialized as they are detected by the receiver.
8. Limiting values
Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO Tstg Vesd Parameter supply voltage input voltage output voltage storage temperature electrostatic discharge voltage HBM MM CDM
[1] [2] [3]
[1] [2] [3]
Conditions receiver driver
Min -0.3 -0.3 -0.3 -65 -
Max +3.0 VDD + 0.5 VDD + 0.5 +150 1500 200 1000
Unit V V V C V V V
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Machine Model: ANSI/EOS/ESD-S5.2.1-1999, standard for ESD sensitivity testing, Machine Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3.1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 15. Symbol VDD VI IOH IOL Tamb Recommended operating conditions Parameter supply voltage input voltage HIGH-level output current LOW-level output current ambient temperature 0.8 x VDD 0.2 x VDD operating in free air Conditions Min 1.65 0 -40 Typ 1.8 Max 1.95 VDD -1 1 +85 Unit V V mA mA C
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10. Static characteristics
Table 16. Static characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol VDD VIH VIL VOH VOL Ci IDD Parameter supply voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input capacitance supply current II = -10 A II = 10 A IO = -1 mA IO = 1 mA TX mode Shutdown mode; Tamb = -40 C to +60 C Standby mode; Tamb = -40 C to +60 C Active mode PCLK = 6 MHz; Mode 00 PCLK = 12 MHz; Mode 00 PCLK = 20 MHz; Mode 00 PCLK = 8 MHz; Mode 01 PCLK = 22 MHz; Mode 01 PCLK = 40 MHz; Mode 01 PCLK = 20 MHz; Mode 10 PCLK = 40 MHz; Mode 10 PCLK = 65 MHz; Mode 10 Transmitter mode, FSS mode (TX/RX = HIGH; FSS = HIGH) IDD supply current Shutdown mode; Tamb = -40 C to +60 C Standby mode; Tamb = -40 C to +60 C Active mode PCLK = 6 MHz; Mode 00 PCLK = 12 MHz; Mode 00 PCLK = 20 MHz; Mode 00 PCLK = 8 MHz; Mode 01 PCLK = 22 MHz; Mode 01 PCLK = 40 MHz; Mode 01 PCLK = 20 MHz; Mode 10 PCLK = 40 MHz; Mode 10 PCLK = 65 MHz; Mode 10
[1] [1]
Conditions
Min 1.65 0.7VDD 0 0.8VDD 0 -
Typ 1.8 2 4 4
Max 1.95 VDD 0.3VDD VDD 0.2VDD 4 10 10
Unit V V V V V pF A A
Transmitter mode, PSS mode (TX/RX = HIGH; FSS = LOW)
-
11 15 21 13 19 26 19 26 35 4 4
12.6 17.3 23.5 14.8 21.2 29.3 21.1 28.8 36.8 10 10
mA mA mA mA mA mA mA mA mA A A
-
12 17 24 13 20 28 19 26 35
13.7 19.2 26.6 14.9 22.3 31.9 21.2 29.1 38.9
mA mA mA mA mA mA mA mA mA
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Table 16. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol IDD Parameter supply current Conditions LOW)[2] [1]
Min
Typ 4 4
Max 10 10
Unit A A
Receiver mode, PSS mode (TX/RX = LOW; FSS =
Shutdown mode; Tamb = -40 C to +60 C Standby mode; Tamb = -40 C to +60 C Active mode PCLK = 6 MHz; Mode 00 PCLK = 12 MHz; Mode 00 PCLK = 20 MHz; Mode 00 PCLK = 8 MHz; Mode 01 PCLK = 22 MHz; Mode 01 PCLK = 40 MHz; Mode 01 PCLK = 20 MHz; Mode 10 PCLK = 40 MHz; Mode 10 PCLK = 65 MHz; Mode 10
[1]
8 14 22 8.5 16 25 14 22.5 34 4 4
10.7 16.5 25 11 19.5 31 17.8 28 40 10 10
mA mA mA mA mA mA mA mA mA A A
Receiver mode, FSS mode (TX/RX = LOW; FSS = HIGH)[2] IDD supply current Shutdown mode; Tamb = -40 C to +60 C Standby mode; Tamb = -40 C to +60 C Active mode PCLK = 6 MHz; Mode 00 PCLK = 12 MHz; Mode 00 PCLK = 20 MHz; Mode 00 PCLK = 8 MHz; Mode 01 PCLK = 22 MHz; Mode 01 PCLK = 40 MHz; Mode 01 PCLK = 20 MHz; Mode 10 PCLK = 40 MHz; Mode 10 PCLK = 65 MHz; Mode 10
[1] [2]
-
7.5 13 20.6 8.1 15.4 23.4 13.5 21.8 33
10.2 15.5 23.6 10.6 18.6 29.3 17.3 26.9 38
mA mA mA mA mA mA mA mA mA
Worst-case data pattern for power dissipation is used: alternating vertical stripes. The colors of the stripes correspond to the data pattern: RGB[23:0] = 0xAA AAAA (odd stripes) / RGB[23:0] = 0x55 5555 (even stripes). Based on receiver output load (per output) of 16 pF. The loaded outputs are: PCLK, R[7:0], G[7:0], B[7:0], HS, VS and DE.
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11. Dynamic characteristics
11.1 Transmitter mode
Table 17. Dynamic characteristics for Transmitter mode VDD = 1.65 V to 1.95 V, Tamb = -40 C to +85 C, unless otherwise specified. All CMOS input signals' rise time and fall time to Transmitter are stipulated to be from 1 ns to 15 ns. Symbol fi(PCLK) Parameter input frequency on pin PCLK Conditions Mode 00; see Table 5 Mode 01; see Table 5 Mode 10; see Table 5 i(PCLK) input duty cycle on pin PCLK Min 4.0 8.0 20.0 33 2.0 2.0 PCLK -3 dB corner frequency of PLL loop filter response -300 Typ Max 21.6 43.3 65.0 67 +300 Unit MHz MHz MHz % TPCLK ns ns ps
tsu(D-PCLK) set-up time from data input to PCLK th(D-PCLK) tjit(cc) BPLL(loop) hold time from data input to PCLK cycle-to-cycle jitter time PLL loop bandwidth
0.02 x fi(PCLK) 0.03 x fi(PCLK) 0.05 x fi(PCLK) MHz
VS, HS, DE, R[7:0], G[7:0], B[7:0]
0.7VDD 0.3VDD tsu(D-PCLK) th(D-PCLK)
0.7VDD PCLK 0.3VDD
002aab367
Fig 19. AC timing diagram - Transmitter mode
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11.2 Receiver mode
Table 18. Dynamic characteristics for Receiver mode VDD = 1.65 V to 1.95 V, Tamb = -40 C to +85 C, unless otherwise specified. CMOS output load CL = 16 pF. Symbol fo(PCLK) Parameter output frequency on pin PCLK Conditions Mode 00; see Table 5 Mode 01; see Table 5 Mode 10; see Table 5 o(PCLK) output duty cycle on pin PCLK Mode 00 or Mode 10; F/XS = 1 Mode 01; F/XS = 1 tsk(Q) data output skew time Mode 00; F/XS = 1 Mode 01; F/XS = 1 Mode 10; F/XS = 1 Mode 00; F/XS = 0 Mode 01; F/XS = 0 Mode 10; F/XS = 0 tjit(r)PCLK tr PCLK rise jitter time rise time CMOS signals Mode 00; F/XS = 0 Mode 00; F/XS = 1 Mode 01; F/XS = 0 Mode 01; F/XS = 1 Mode 10; F/XS = 0 Mode 10; F/XS = 1 tf fall time CMOS signals Mode 00; F/XS = 0 Mode 00; F/XS = 1 Mode 01; F/XS = 0 Mode 01; F/XS = 1 Mode 10; F/XS = 0 Mode 10; F/XS = 1 BPLL(loop) PLL loop bandwidth -3 dB corner frequency of PLL loop filter response 8 4 4 1 4 1 18 10 10 3 10 3 ns ns ns ns ns ns 8 4 4 1 4 1 18 10 10 3 10 3 ns ns ns ns ns ns Min 4.0 8.0 20.0 45 48 -0.5 -0.5 -0.5 -3.0 -0.5 -1.4 -0.6 Typ 50 53 0 0 0 0 0 0 0 Max 21.6 43.3 65.0 55 59 1.5 0.8 0.8 2.0 2.5 3.0 0.6 Unit MHz MHz MHz % TPCLK % TPCLK ns ns ns ns ns ns ns
0.09 x fo(PCLK) 0.11 x fo(PCLK) 0.14 x fo(PCLK) MHz
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VS, HS, DE, R[7:0], G[7:0], B[7:0]
0.8VDD 0.2VDD tsk(Q) tjit(r)PCLK 0.8VDD
PCLK 0.2VDD
002aab368
Fig 20. AC timing diagram - Receiver mode
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11.3 Power-on/power-off sequence
11.3.1 Power-on sequence
Table 19. Power-on sequence timing characteristics VDD = 1.65 V to 1.95 V, Tamb = -40 C to +85 C, unless otherwise specified. These values are for transitions of the Shutdown mode to the Standby mode and the Standby mode to the Active mode. Symbol tsu(VDDH-XSDH) tsu(XSDH-PCLKV) td(PCLKH-DV) td(XSDH-stb) td(RXDV-RXQV) Parameter set-up time from VDD HIGH to XSD HIGH set-up time from XSD HIGH to PCLK valid delay time from PCLK HIGH to data valid delay time from XSD HIGH to standby delay time from receiver data input valid to receiver data output valid Conditions Transmitter mode Receiver mode Transmitter mode Transmitter mode Receiver mode Receiver mode Min 0 0 10 Typ Max 2 10 2 Unit ms ms s ms s ms
VDD
tsu(VDDH-XSDH) 0.7VDD provided
XSD
tsu(XSDH-PCLKV)
Transmitter mode PCLK stopped td(PCLKH-DV) high-speed signal outputs high-Z valid
VDD
tsu(VDDH-XSDH)
XSD Power mode
td(XSDH-stb) Standby
Shutdown Receiver mode high-speed signal inputs high-Z
valid td(RXDV-RXQV)
all data outputs and PCLK
defined in the Shutdown or Standby mode
valid outputs reflecting high-speed channels
002aab369
Fig 21. Power-on sequence of the link
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11.3.2 Power-off sequence
Table 20. Power-off sequence timing characteristics VDD = 1.65 V to 1.95 V, Tamb = -40 C to +85 C, unless otherwise specified. These values are for transition of the Active mode to the Standby mode. Symbol td(PCLKL-TXQZ) td(RXDZ-RXQinact) th(XSDL-VDDL) Parameter delay time from PCLK LOW to transmitter data output float receiver data input float to receiver data output inactive delay time supply voltage LOW after XSD LOW hold time Conditions Transmitter mode Receiver mode Transmitter mode Receiver mode Min 0 0 Typ Max 100 5 Unit s s ms ms
provided Transmitter mode PCLK
stopped td(PCLKL-TXQZ)
Transmitter mode high-speed signal outputs
valid
high-impedance
Transmitter mode XSD th(XSDL-VDDL) Transmitter mode VDD
0.3VDD
Receiver mode high-speed signal inputs
valid
high-impedance
td(RXDZ-RXQinact) R[7:0], G[7:0], B[7:0], VS, HS Receiver mode all outputs valid outputs reflecting high-speed channels defined in the Shutdown mode or Standby mode DE, PCLK
Receiver mode XSD th(XSDL-VDDL) Receiver mode VDD
002aab370
0.3VDD
Fig 22. Power-off sequence of the link
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11.4 High-speed signaling channel
Table 21. High-speed signaling channel SubLVDS output characteristics, Transmitter mode VDD = 1.65 V to 1.95 V, Tamb = -40 C to +85 C, unless otherwise specified. See Section 13.1 for testing information. Symbol VO(dif) VO(cm) Parameter differential output voltage common-mode output voltage Conditions see Figure 26 see Figure 26 see Figure 27 Min 100 0.8 -75 Typ 150 0.9 Max 200 1.0 +75 Unit mV V mV
VO(cm)ripple(p-p) peak-to-peak ripple common-mode output voltage Ro(dif) differential output resistance differential rise time differential fall time operating frequency output current relative differential output voltage difference common-mode output voltage difference rise time difference fall time difference output leakage current bit time from CLK HIGH to data output
between complimentary outputs of any differential pair: CLK+/CLK-; D0+/D0-; D1+/D1-; D2+/D2- from 20 % to 80 % of VO(dif); see Figure 28 from 80 % to 20 % of VO(dif); see Figure 28 output drive current per channel between CLK+/CLK- and Dn+/Dn-, referenced to CLK+/CLK- between CLK+/CLK- and Dn+/Dn- tr(CLK+/CLK-) - tr(Dn+/Dn-) tf(CLK+/CLK-) - tf(Dn+/Dn-) Shutdown or Standby mode (high-impedance state) PSS mode; Mode 00 or Mode 01; see Table 5, Figure 31 PSS mode: Mode 10; see Table 5, Figure 31
[2][3] [1]
80
180
280
tr(dif) tf(dif) foper IO VO(dif)/VO(dif)
200 200 -10
-
500 500 325 4 +10
ps ps MHz mA %
VO(cm) tr tf ILO tbit(CLKH-Q)
-0.1 -100 -100 -3.0
-
+0.1 +100 +100 +3.0
V ps ps A
N x UI N x UI N x UI ps - 19 % x UI + 19 % x UI N x UI N x UI N x UI ps - 16 % x UI + 16 % x UI -16 % x UI 0 +16 % x UI ps
[2][3]
tsk(CLK-Q)
CLK edge to data output skew time
FSS mode; see Figure 33
[2]
[1] [2]
V O ( dif )CLK - V O ( dif )DATA [ % ] = ---------------------------------------------------------------- x 100 % V O ( dif )CLK
Mode 00: UI = PCLK period / 30 Mode 01: UI = PCLK period / 15 Mode 10: UI = PCLK period / 10 N is defined as the bit position, where 0 N 29 (Mode 00), 0 N 14 (Mode 01) or 0 N 9 (Mode 10).
[3]
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Table 22. High-speed signaling channel SubLVDS input characteristics, Receiver mode VDD = 1.65 V to 1.95 V, Tamb = -40 C to +85 C, unless otherwise specified. See Section 13.1 for testing information. Symbol VI(dif) Vth(H)i(dif) Vth(L)i(dif) VI(cm) Parameter differential input voltage differential input HIGH-level threshold voltage differential input LOW-level threshold voltage Conditions see Figure 29 see Figure 30 see Figure 30 Min 70 +25 0.4 -75 80 between CLK+/CLK- and Dn+/Dn-, referenced to CLK+/CLK-
[1]
Typ 100 100 -
Max 200 -25 1.4 +75 120 800 800 325 +10
Unit mV mV mV V mV ps ps MHz %
common-mode input voltage see Figure 29
see Figure 27 VI(cm)ripple(p-p) peak-to-peak ripple common-mode input voltage Ri(dif) tr(dif) tf(dif) foper VI(dif)/VI(dif) differential input resistance differential rise time differential fall time operating frequency relative differential input voltage difference internal termination resistor; see Figure 29 from 20 % to 80 % of VI(dif); see Figure 28 from 80 % to 20 % of VI(dif); see Figure 28
-10
VI(cm) tr tf Rpd
common-mode input voltage between CLK+/CLK- and difference Dn+/Dn- rise time difference fall time difference pull-down resistance tr(CLK+/CLK-) - tr(Dn+/Dn-) tf(CLK+/CLK-) - tf(Dn+/Dn-) complimentary input (Dn-) to GND; input clock inactive; see Figure 29 Shutdown or Standby mode PSS mode; see Figure 32
[2][3]
-0.1 -100 -100 -
1
+0.1 +100 +100 50
V ps ps k
ILI tbit(CLKH-D) tsk(CLK-D)
input leakage current bit time from CLK HIGH to data input
-90
-
+90
A
N x UI N x UI N x UI ps - 21 % x UI + 21 % x UI -21 % UI 0 +21 % UI ps
CLK edge to data input skew FSS mode; see Figure 33 time
[2]
[1] [2]
V I ( dif )CLK - V I ( dif )DATA [ % ] = ------------------------------------------------------------- x 100 % V I ( dif )CLK
Mode 00: UI = PCLK period / 30 Mode 01: UI = PCLK period / 15 Mode 10: UI = PCLK period / 10 N is defined as the bit position, where 0 N 29 (Mode 00), 0 N 14 (Mode 01) or 0 N 9 (Mode 10).
[3]
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12. Application information
12.1 Typical lane and PCLK configurations
The PTN3700 supports PCLK (pixel clock) frequencies from 4 MHz to 65 MHz over 1, 2 or 3 data lanes. Table 23 shows the typical number of data lanes needed, assuming blanking overhead of 20 %. Note that 20 % overhead is an example value for illustration/calculation purposes only and not a requirement.
Table 23. Panel Typical PCLK and number of data lanes Horizontal Vertical Color Other bit bits 18 18 18 24 24 24 24 24 24 12 12 12 6 6 6 6 6 6 Frame rate (Hz) 60 60 60 60 60 60 60 60 60 Blanking overhead 20 % 20 % 20 % 20 % 20 % 20 % 20 % 20 % 15 % Pixel clock (MHz) 5.5 6.9 10.5 11.1 22.1 29.5 34.6 56.6 63.6 Serial aggregate data rate (Mbit/s) 1-lane 165.9 207.4 316.3 331.8 316.3 331.8 663.6 885.4 1036.8 663.6 885.4 1036.8 1698.7 1909.7 2-lane 3-lane
QVGA WQVGA CIF+ HVGA VGA WVGA SVGA XGA 720p
240 400 352 320 640 854 800 1024 1280
320 240 416 480 480 480 600 768 720
12.2 Pin configurations for various topologies of PCB
There are two input pins, PSEL1 and PSEL0, on the PTN3700 that allow for pinning order configurations. PSEL1 will change the pinning order of the serial signals, and allow for various topologies of PCB or flex layout without crossing the high-speed differential traces. The example shown in Figure 23 has set PSEL1 = 0 at receiver side, and PSEL1 = 1 at the transmitter to avoid the traces crossing. Figure 24 shows another configuration, which has PSEL1 = 1 at receiver, and PSEL1 = 0 at transmitter. PSEL0 can configure the pinning order of the parallel signals, and enables the easy introduction of the PTN3700 into an existing parallel design avoiding board re-layout. Figure 23 and Figure 24 show two configuration examples.
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R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 PCLK HS VS DE
Transmitter mode PSEL1 = 1 PSEL0 = 0
Receiver mode PSEL1 = 0 PSEL0 = 0
ball A1 index G7 G6 G5 G3 G1 B7 B5 B4 R1 R0 G4 G2 G0 B6 B3 B2 R3 R2 VDD FSS FM VDD B1 B0 R5 R4 GND LS1 LS0 GND PCLK HS R7 R6 A0 CPO XSD F/XS D2+ D2- D1+ D1- CLK+ D2+ D2- D1+ D1- CLK+ CLK- D0+ D0- ball A1 index VDDA GNDA TX/RX VDD R7 R6 A1 PSEL0 R5 R4 GND LS0 LS1 GND PCLK HS R3 R2 VDD FM FSS VDD B1 B0 R1 R0 G5 G3 G1 B7 B3 B2 G7 G6 G4 G2 G0 B6 B5 B4
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 PCLK HS VS DE
002aac935
PSEL1 GND PSEL0 A1 VS DE VDD
GND PSEL1 F/XS XSD CPO A0 VS DE
TX/RX CLK- GNDA VDDA D0+ D0-
Transparent top view.
Fig 23. Pinning configuration example 1
B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 PCLK HS VS DE
Transmitter mode PSEL1 = 0 PSEL0 = 1
Receiver mode PSEL1 = 1 PSEL0 = 1
ball A1 index G0 G1 G2 G4 G6 R0 R2 R3 B6 B7 G3 G5 G7 R1 R4 R5 B4 B5 VDD FSS FM VDD R6 R7 B2 B3 GND LS1 LS0 GND PCLK HS B0 B1 A0 CPO XSD F/XS D0- D0+ CLK- CLK+ D1- D1+ D2- D2+ ball A1 index D0- D0+ VDDA GNDA B0 B1 A1 PSEL0 B2 B3 GND LS0 LS1 GND PCLK HS B4 B5 VDD FM FSS VDD R6 R7 B6 B7 G2 G4 G6 R0 R4 R5 G0 G1 G3 G5 G7 R1 R2 R3
B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 PCLK HS VS DE
002aac936
CLK- TX/RX CLK+ D1- D1+ D2- D2+ VDD
PSEL1 GND PSEL0 A1 VS DE VDD TX/RX GNDA VDDA
GND PSEL1 F/XS XSD CPO A0 VS DE
Transparent top view.
Fig 24. Pinning configuration example 2
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12.3 Power decoupling configuration
The PTN3700 needs 1.8 V VDD and 1.8 V VDDA. Both can share the same voltage regulator, and use a 10 resistor for isolation. The recommended power configuration of the decoupling is shown in Figure 25. It is recommended to install one 0.1 F ceramic capacitor for each VDD pin and one 0.01 F ceramic capacitor for VDDA pin, and the lead length between the IC power pins and decoupling capacitors should be as short as possible.
10
VDD
0.1 F 0.1 F 0.1 F 0.01 F
VDDA
002aac937
Fig 25. Power decoupling configuration
12.4 PCB/Flex layout guideline
The high data rate at the serial I/O requires some specific implementations in the PCB and flex layout design. The following practices can be used as guideline:
* The differential pair must be routed symmetrically. Keep all four pairs of differential
signal traces the same length. The difference in trace length should be less than 20 mils.
* Maintain 100 differential impedance. * Do not route signals over any plane split; use only one ground plane underneath the
differential signals.
* Avoid any discontinuity for signal integrity. Differential pairs should be routed on the
same layer and the number of vias on the differential traces should be minimized. Test points should be placed in series and symmetrically. Stubs should not be introduced on the differential pairs.
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13. Test information
13.1 High-speed signaling channel measurements
+ CLK, D0, D1 or D2 - VO(dif)
49.9 1 %
49.9 1 %
VO(cm)
002aac101
Fig 26. Transmitter termination and definition for measurement of electrical parameters
Dn+, CLK+ VI(cm), VO(cm) Dn-, CLK- VI(cm)ripple(p-p), VO(cm)ripple(p-p)
002aac102
Fig 27. Voltage waveforms, common mode ripple measurement (single-ended mode)
tf(dif) VI(dif), VO(dif)
20 %
tr(dif)
60 %
0V
20 %
002aac103
Fig 28. Voltage waveforms, differential input or output voltage and rise and fall time measurements
receiver
Ri(dif)
VI(dif) VI(cm)
Rpd
002aac104
Fig 29. Receiver measurement definition for measurement of electrical parameters
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differential (Dn+ - Dn-), (CLK+ - CLK-)
Vth(H)i(dif) Vth(L)i(dif)
0V
002aac105
Fig 30. Voltage waveforms, input threshold voltage measurements
CLK (differential) tbit(CLKH-Q) bit N tbit(CLKH-Q) bit 1 tbit(CLKH-Q) bit 0 D0, D1 or D2 (differential) bit 0 bit 1 bit N
0V
0V
002aac106
Fig 31. Transmitter high-speed serial outputs timing relationships (PSS mode)
CLK (differential) tbit(CLKH-D) bit N tbit(CLKH-D) bit 1 tbit(CLKH-D) bit 0 D0, D1 or D2 (differential) bit 0 bit 1 bit N
0V
0V
002aac806
Fig 32. Receiver high-speed serial inputs timing relationships (PSS mode)
CLK (differential)
0V
D0, D1 or D2 (differential) tsk(CLK-Q), tsk(CLK-D) tsk(CLK-Q), tsk(CLK-D)
0V
002aac807
Fig 33. Transmitter and receiver high-speed serial outputs and inputs timing relationships (FSS mode)
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14. Package outline
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 x 4.5 x 0.65 mm SOT991-1
D
B
A
ball A1 index area E A A2 A1 detail X
e1 e b v w
M M
CAB C
C y1 C y
H G F E D C B A
e 1/2 e
e2
ball A1 index area
1
2
3
4
5
6
7
X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1 A1 0.25 0.15 A2 0.75 0.60 b 0.35 0.25 D 4.1 3.9 E 4.6 4.4 e 0.5 e1 3 e2 3.5 v 0.15 w 0.05 y 0.08 y1 0.1
OUTLINE VERSION SOT991-1
REFERENCES IEC --JEDEC --JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-02-06 07-02-07
Fig 34. Package outline SOT991-1 (VFBGA56)
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15. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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15.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 35) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 24 and 25
Table 24. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 25. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 35.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 35. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
16. Abbreviations
Table 26. Acronym CIF CMOS DDR EMI fps HVGA I/O LVDS MSB PCB PLL QVGA RGB SMILi SubLVDS SVGA UI VGA WQVGA
PTN3700_1
Abbreviations Description Common Intermediate Format Complementary Metal Oxide Semiconductor Double Data Rate ElectroMagnetic Interference frames per second Half-size Video Graphics Array Input/Output Low-Voltage Differential Signalling Most Significant Bit Printed-Circuit Board Phase-Locked Loop Quarter Video Graphics Array Red/Green/Blue Simple Mobile Interface Link Sub Low-Voltage Differential Signalling Super Video Graphics Array Unit Interval Video Graphics Array Wide Quarter Video Graphics Array
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Abbreviations ...continued Description Wide Video Graphics Array eXtended Graphics Array eXtended Video Graphics Array
Table 26. Acronym WVGA XGA XVGA
17. Revision history
Table 27. Revision history Release date 20070814 Data sheet status Product data sheet Change notice Supersedes Document ID PTN3700_1
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18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
19. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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20. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.3.1 7.4.3.2 7.4.4 7.4.4.1 7.4.4.2 7.5 7.6 7.7 7.8 8 9 10 11 11.1 11.2 11.3 11.3.1 11.3.2 11.4 12 12.1 12.2 12.3 12.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 9 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Link programmability. . . . . . . . . . . . . . . . . . . . 10 Versatile signal mirroring programmability . . . 10 High-speed data channel protocol options . . . 12 Serial protocol bit mapping - pseudo source synchronous mode (FSS = LOW). . . . . . . . . . 13 Serial protocol bit mapping - fully source synchronous mode (FSS = HIGH) . . . . . . . . . 14 PLL, PCLK, CLK and pixel synchronization . . 15 Pixel synchronization . . . . . . . . . . . . . . . . . . . 15 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 HS, VS and DE signal usage in various PTN3700 modes. . . . . . . . . . . . . . . . . . . . . . . 15 PSS mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FSS mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 17 Link error detection and correction . . . . . . . . . 18 Frame Mixing and Advanced Frame Mixing . . 19 Auxiliary signals . . . . . . . . . . . . . . . . . . . . . . . 20 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20 Recommended operating conditions. . . . . . . 20 Static characteristics. . . . . . . . . . . . . . . . . . . . 21 Dynamic characteristics . . . . . . . . . . . . . . . . . 23 Transmitter mode . . . . . . . . . . . . . . . . . . . . . . 23 Receiver mode . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-on/power-off sequence . . . . . . . . . . . . 26 Power-on sequence . . . . . . . . . . . . . . . . . . . . 26 Power-off sequence . . . . . . . . . . . . . . . . . . . . 27 High-speed signaling channel. . . . . . . . . . . . . 28 Application information. . . . . . . . . . . . . . . . . . 30 Typical lane and PCLK configurations . . . . . . 30 Pin configurations for various topologies of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power decoupling configuration . . . . . . . . . . . 32 PCB/Flex layout guideline. . . . . . . . . . . . . . . . 32 13 13.1 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 Test information. . . . . . . . . . . . . . . . . . . . . . . . High-speed signaling channel measurements Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 35 36 36 36 36 37 38 39 40 40 40 40 40 40 41
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
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All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 August 2007 Document identifier: PTN3700_1

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